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//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// Configuration and timing definitions for simulations of the M8051W/EW core
// 
// $Log: m8051w_tb_cfg.v,v $
// Revision 1.3  2002/01/09
// Final testbench changes for version2
//
// Revision 1.2  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.1  2001/11/14
// First EW checkin
//
// Revision 1.1  2001/10/08
// Name changes for VHDL cosim
//
// Revision 1.6  2001/07/10
// Tidy up
//
// Revision 1.5  2001/04/27
// update of the CVS repository
//
// Revision 1.4  2000/12/13
// Simulation exit address updated
//
// Revision 1.3  2000/05/19
// Change of Exit address to 20FD hex, and to exclude OCI
//
// Revision 1.2  2000/03/28
// OCI update
//
// Revision 1.1  2000/03/06
// Revised configuration scheme
//
////////////////////////////////////////////////////////////////////////////////
//
// Purpose      :       Configuration, timing and simulation control parameters
//              :       used by the M8051W/EW Soft Core testbench.
//
//
// NOTE:  Timing parameters should be no smaller than the equivalent parameters 
// in the synthesis constraint file "hier_setup.scr".
// Simulations should be run at 10MHz for correlation against RTL reference
// listings.  Running gate-level simulations at maximum clock speed results in
// output delays that exceed the half-clock period strobe interval.
//
////////////////////////////////////////////////////////////////////////////////

// Time units are specified in nanoseconds
`timescale 1 ns / 1 ps

// Test Bench Time Constants

`define Thclk 50                     // half period for clock input
`define Tclk  (`Thclk * 2)
`define Ttres `Tclk                  // Test reset pulse width
`define Tres  (`Tclk * 4.0)          // Compatible (sampled) reset pulse width

// Simulation settings

`define TstrobeOffset (`Thclk * 0.9) // output sampling time for listings
`define Tmaxrun 500000000              // limit failure mode run time 5msec
`define Timer2b_maxrun 125000000     // Timer2b max simulation time 125msec
`define EXIT_ADDRESS 16'h20FE   // exit vector for current test program
// The Exit_Address for the test programs has as follows
// Timer2b.asm -> EXIT_ADDRESS=20FEh
// Timer2.asm  -> EXIT_ADDRESS=20FEh
// Memory0.asm -> EXIT_ADDRESS=FFE0h
// Selft.asm   -> EXIT_ADDRESS=20FEh
`define BadData 8'hFF           // define memory output during address decoding
`define CORRELATE               // make a listing for discrete part correlation
`define OPC_CORRELATE           // make a list of opcodes executed

// Internal data memory (IRAM) specification

`define Tiramacc  (`Tclk * 0.5)              // Fixed fraction of clock cycle
`define Tiramwwdo (`Tclk * 0.5)              // Write propagation delay
`define Tiramasw  0.3:0.5:0.7                // Example setup and hold constants
`define Tiramah   0.07:0.11:0.16             // Example address hold
`define Tiramdw   1.39:1.95:2.94             // Example data setup
`define Tiramdh   0.02:0.03:0.05             // Example data hold 
`define IramSize  256                        // Example IRAM array size (bytes)
`define IramLines 8                          // Number of IRAM address lines

// Program ROM specification

`define Tromacc    (`Tclk * 0.5)             // Example ROM access time
`define Tromoe     (`Tclk * 0.1)             // Example ROM drive enable delay
`define RomSize    'h10000                   // Example ROM array size (bytes)
`define RomALines  16                        // Number of ROM address lines
`define ProgramWaitStates 4'h0               // Number of extra clock cycles
`define ProgramWriteWaitStates 4'h0          // Number of extra clock cycles
                                             // during program writes
`define Twait      (`Tclk * 0.4)

// External data memory (XRAM) specification

`define Txramacc   (`Tclk * 0.5)             // Example XRAM access time
`define Txramoe    (`Tclk * 0.1)             // Example XRAM drive enable delay
`define XramSize   'h10000                  // Example XRAM array size (bytes)
`define XramALines 16                        // Number of XRAM address lines
`define XramWaitStates 4'h0                  // Number of extra clock cycles
`define Uninitialised 8'hff                  // Reset value for memory cells

// Testbench external SFR address definitions

`define Addr_ESFR0 8'hC0         // External interrupt sources 5 - 12 
`define Addr_ESFR1 8'hC1         // External interrupt source 13 and NMI
`define Addr_WCON  8'hFE         // Wait state generator time constants
`define Addr_CFG1  8'hFF         // E-Warp core configuration status register
`define Addr_CFG2  8'hFD         // E-Warp core configuration status register

// Test bench configuration options

  //`define IncludeOCI             // Include the Debugger OCI within the wrapper
  `define ExternalSFR            // Include some example ESFRs
  `define ClockGating            // Use behavioural model of clock gating

